1. Technical Field
The present invention relates to a power source stabilization circuit, an electronic device, and a testing apparatus.
2. Related Art
It is known in the art to stabilize a power source voltage that is supplied to an operational circuit of an electronic device such as a semiconductor circuit by connecting a pass capacitor to a power source wiring that inputs the power to the electronic device (for example, see Patent Document 1). Generally, the pass capacitor is provided outside the chip of the electronic device and located between the ground potential and the power source wiring.    Patent Document 1: Japanese Patent Application Publication No. 07-333249
Accordingly, the fluctuation in the current flowing through the power source wiring is reduced by supplying to the electronic device via the power input terminal a current determined by the fluctuation in the current consumed by the electronic device. In this manner, the fluctuation in the power source voltage caused by the fluctuation in the current can be reduced. The pass capacitor used commonly has a capacitance of approximately several dozen nF to several μF.
However, the power source voltage may fluctuate while traveling the wiring from the power input terminal of the electronic device to the operational circuit due to the fluctuation in the current consumed by the operational circuit. Such a fluctuation in the power source voltage cannot be compensated for by means of the above-described pass capacitor, which is provided outside the chip of the electronic device.
To address this issue, a similar pass capacitor may be additionally provided within the chip of the electronic device. Such a capacitor inside the chip of the electronic device may be formed by using the gate capacitance of a transistor. Here, a single transistor only has a gate capacitance of approximately several fF. Therefore, an enormous number of elements needs to be formed to form the above-mentioned pass capacitor within the chip.